Functional Description of FX1N-32MT Product
Purchase Notes:
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The board is supplied by 24V DC. Do not input AC or 220V.
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The board uses serial port download program.
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project |
performance |
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Operation control method |
Stored program repeatedly scanning mode |
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Input and output control mode |
Batch mode (when executing END instruction), input and output refresh command, pulse capture function |
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Programming language |
Ladder diagram, SFC stepping instructions |
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Ladder programming software |
GX Developer, GX Works2 |
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Program memory |
8K step EEPROM |
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Type of instruction |
Direct instruction |
27 |
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Step ladder instruction |
2 |
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Basic application instruction |
70 |
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Instructions speed |
Basic instructions |
0.1μS-0.55μS instruction |
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Application instructions |
0.8μS-10μS instruction |
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input Output |
Input relay X |
X0-X127,128 points |
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Output relay Y |
Y0-Y127,128 poinst |
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Auxiliary relay M |
General use |
M0-M1523,1524 points |
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Special use |
M8000-M1535,1152 points( after M500 Power down save) |
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State S |
S10-S999,1000 points |
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Timer T |
100MS |
T0-199,200 points |
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10MS |
T200-T245,46 points |
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1MS |
T246-T249,4 points |
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100MS accumulation |
T250-T255,6 points |
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Counter C |
Counter 16 bits |
C0-C199,200point(after C100 Power down save) |
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Counter 32 bits |
C200-C255,56 points |
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Data register |
General use |
D0-D500(after D200 Power down save),500point |
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Special use |
D8000-D8255,255 points |
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Indexing |
V7-V0,Z7-Z0,16 points |
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Nested pointer |
P0-P127,128 points |
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constant |
K 16 bit |
-32768-32767 |
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K 32 bit |
-2 147 483 648-2 147 483 647 |
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H 16 bit |
0-FFFF |
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H 32 bit |
0-FFFFFFFF |
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Support instruction set
27 basic instructions
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Mnemonic, name |
function |
Available Soft Components |
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[LD] take |
Operation start“a”contact |
XYMSTC |
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[LD] take reverse |
Operation start“b”contact |
XYMSTC |
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[LDP] take pulse rising edge |
The rising edge detects the start of the operation |
XYMSTC |
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[LDF] take the pulse falling edge |
The falling edge detects the start of the operation |
XYMSTC |
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[AND] and |
Series“a”contact |
XYMSTC |
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[ANI] and reversal |
Series“b”contact |
XYMSTC |
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[ANDP] with pulse rising edge |
The rising edge detects“a”series connection |
XYMSTC |
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[ANDF] with pulse falling edge |
Falling edge detects serial connection |
XYMSTC |
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[OR] or |
Parallel“a”contact |
XYMSTC |
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[ORI] or inversion |
Parallel“b”contact |
XYMSTC |
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[ORP] or pulse rising edge |
The rising edge detects a parallel connection |
XYMSTC |
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[OUT]output |
Coil drive command |
YMSTC |
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[SET] set |
Coil hold command |
YMS |
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[RST]Reset |
Coil reset command |
YMSTCD |
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[PLS] rising edge pulse |
Rising edge detection command |
YM |
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[PLF] rising edge pulse |
Falling edge detection instruction |
YM |
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[MC] Master |
Connecting coil of common series point |
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[MCR] master reset |
Clearing coil of common series point |
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[MPS] onto the stack |
Operational storage |
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[MRD] read stack |
Storage readout |
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[MPP] popping |
Save read and reset |
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[INV]Reverse |
Reverse of operation result |
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[NOP] empty operation |
No action |
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[END] end |
End of sequence program |
Two step ladder diagram instructions
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STL step ladder |
Step ladder start |
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RET return |
Step ladder end |
Application instruction
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classification |
FNC NO. |
Instruction mnemonic |
Instruction name |
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High speed processing |
56 |
SPD |
Pulse density |
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57 |
PLSY |
Pulse output |
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59 |
PLSR |
Adjustable speed pulse output |
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Easy command |
66 |
ALT |
Alternate output |
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67 |
RAMP |
Ramp signal |
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Positioning |
156 |
ZRN |
Origin return |
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157 |
PLSV |
Variable pulse output |
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158 |
DRVI |
Corresponding position control |
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159 |
DRVA |
Absolute position control |
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Contact comparison instruction |
224 |
LD= |
Start of operation (S1) = (S2) turn on |
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225 |
LD﹥ |
Start of operation (S1) ﹥(S2) turn on |
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226 |
LD﹤ |
Start of operation (S1) ﹥(S2) turn on |
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228 |
LD﹤﹥ |
Start of operation (S1) ≠(S2) turn on |
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229 |
LD﹤= |
Start of operation (S1) ≤(S2) turn on |
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230 |
LD﹥= |
Start of operation (S1) ≥(S2) turn on |
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232 |
AND = |
Series connection (S1) = (S2) conduction |
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233 |
AND﹥ |
Series connection (S1) ﹥(S2) conduction |
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234 |
AND﹤ |
Series connection (S1) ﹥(S2) conduction |
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Contact comparison instruction |
236 |
AND﹤＞ |
Series connection (S1) ≠(S2) conduction |
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237 |
AND﹤= |
Series connection (S1) ≤(S2) conduction |
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238 |
AND＞= |
Series connection (S1) ≥(S2) conduction |
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240 |
OR = |
Parallel connection (S1) = (S2) conduction |
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241 |
OR﹥ |
Parallel connection (S1) ﹥(S2) conduction |
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242 |
OR﹤ |
Parallel connection (S1) ﹥(S2) conduction |
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243 |
OR﹤﹥ |
Parallel connection (S1) ≠(S2) conduction |
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244 |
OR﹤= |
Parallel connection (S1) ≤(S2) conduction |
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245 |
OR﹥= |
Parallel connection (S1) ≥(S2) conduction |
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classification |
FNC NO. |
Instruction mnemonic |
Instruction name |
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Procedure flow chart |
00 |
CJ |
Conditional jump |
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01 |
CALL |
Subroutine call |
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02 |
SRET |
Subroutine return |
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06 |
FEND |
End of main program |
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07 |
WDT |
Watchdog timer |
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08 |
FOR |
Repeat range begins |
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09 |
NEXT |
End of repeat range |
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Transfer and comparison |
10 |
CMP |
Comparison |
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11 |
ZCP |
Regional comparison |
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12 |
MOV |
Transfer |
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15 |
BMOV |
Batch transfer |
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18 |
BCD |
BCD exchange |
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19 |
BIN |
BIN exchange |
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Four arithmetic operations |
20 |
ADD |
BIN addition |
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21 |
SUB |
BIN subtraction |
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22 |
MUL |
BIN multiplication |
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23 |
DIV |
BIN division |
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24 |
INC |
BIN increment |
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25 |
DEC |
BIN decrement |
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26 |
WAND |
Logic and |
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27 |
WOR |
Logical or |
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28 |
WXOR |
Logical XOR |
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Rotation displacement |
34 |
SFTR |
Right shift |
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35 |
SFTL |
Left shift |
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38 |
SFWR |
Shift write |
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39 |
SFRD |
Shift write out |
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Bit processing |
40 |
ZRST |
Reset all |
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41 |
DECO |
decoding |
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42 |
ENCO |
coding |
